1. Field of the Invention
The invention is for improving the performance of a microprocessor system by reducing the skew between the system clock and critical control signals. Reduction in this skew reduces or eliminates the need for waitstates on data accesses to memory devices thereby improving system performance.
2. Prior Art
Improved memory performance in the prior art was accomplished by using higher speed and higher cost, lower density SRAM devices. Custom clock chips with control signals have been developed, but none using a common/generic PAL device and asynchronous state machines.
Prior art methods use higher cost and lower density SRAMs or system performance is sacrificed. Therefore, the overall system cost is higher and the amount of zero waitstate memory available is less than that which is possible by use of the present invention.
For example, referring to FIG. 1 which is a block overview diagram showing how an SRAM might be accessed in the prior art using an Intel 89960KB microprocessor, an 80 MHz oscillator 11 is used to generate a 40 MHz CLK2 signal and a 20 MHz CLK signal using a counter 13 which simply divides the 80 MHz oscillator signal by two (for CLK2) and by four (for CLK). CLK2 and CLK are used to synchronize the transitions between address/data bus states. CLK2 is the clock input to the processor 15 and is double the processor operating frequency. CLK is the operating frequency of the processor.
SRAM 19 is accessed by the microprocessor based upon control signals generated by PALs 17 and by placing an address on the address/data bus which is latched by latch 21 when the signal address latch enable (/ALE) is asserted. Then, depending upon whether a read or write is to take place, as determined by the signal W/R, the addressed location in SRAM 19 is loaded from the address/data bus for a write, or is placed onto the address/data bus from the addressed location for a read. In 80960KB architecture, valid data bytes on the bus are indicated by byte enable signals (BE0, BE1, BE2 and BE3) generated by microprocessor 15. Write enable signals (WE3:WE0) are generated as a function of BE3:BE0 and W/R. That is within a 32 bit word being addressed, WE3:WE0 determine which of the four bytes in the word is to be written.
The details regarding the generation and usage of the four write enable signals, as well as the four output enable signals (OE3:OE0), A3:A2 and SRAMCS generated by PALs 17 for accessing SRAM 19 may be found in a publication of Intel Corporation known as the 80960KB Hardware Developer's Reference Manual. Although the description in the Hardware Developer's Reference Manual is explained using discrete logic gates, a PAL implementation would be readily apparent. The specific generation and usage details are not important for an understanding of the present invention. However, what is important to recognize is that the SRAMCS signal is generated by PALs 17 while the CLK and CLK2 signals are generated by counter 13. In this connection, the signal skew between SRAMCS and CLK2 and CLK created by virtue of the different components used to generate the signals requires additional waitstates when accessing SRAM 19. This skew requires the insertion of one or more waitstates between each data state in a read/write cycle.
For example, assuming four words (i.e., the maximum burst access for an 80960KB processor) of data are to be read from or written to SRAM, there is a one CLK address state followed by four one CLK data states, with each one CLK data state preceded by at least a one CLK waitstate, followed by a one CLK recovery state. Assuming one address state is TA, one data state is TD, one waitstate is TW and one recovery state is TR, the one CLK states for the above example would be TA, TW, TD, TW, TD, TW, TD, TW, TD, TR.